Transistors are multielectrode semiconductor devices in which the current flowing between two specified electrodes is controlled or modulated by the voltage applied at a third (control) electrode. Transistors fall into two major classes: the bipolar junction transistor (BJT) and the field-effect transistor (FET). BJTs were derived from the point-contact transistor, which was invented at Bell Telephone Laboratories in 1947 by Bardeen, Brattain, and Shockley. BJTs comprise two p-n junctions placed back-to-back in close proximity to each other, with one of the regions common to both junctions. This forms either a p-n-p or n-p-n transistor comprising three regions emitter, base and collector. The BJT utilizes the flow of both electrons and holes across the p-n junctions for its electrical behavior. That is, the current flow through the emitter and collector electrodes is controlled by the voltage across the base-emitter p-n junction.
In normal (or forward active) operation of a BJT, the base-emitter p-n junction is forward biased and the base-collector junction is reverse biased. Majority-carrier current flows across the forward-biased emitter-base junction. The emitter is much more heavily doped than the base region, so that most of the total current flow across the base-emitter junction consists of majority carriers from the emitter injected into the base. These injected carriers become minority carriers in the base region, and will tend to recombine. Such recombination is minimized by making the base region very narrow, so that the injected carriers can diffuse across the base to the reverse-biased base-collector junction, where they are swept across the junction into the collector, to appear in the outside circuit as the collector current. The magnitude of this collector current depends on the number of majority carriers injected into the base from the emitter, and thus current is controlled by the base-emitter p-n junction voltage. The output (collector) current is therefore controlled by the input (base-emitter) voltage, and the output circuit of the transistor can be modeled as a voltage-controlled current source (dependent sources), while the input circuit looks like a p-n junction diode.
In principle, the transistor can be operated in reverse active mode by reversing the connections. However, in practice, the transistor is not completely symmetrical. That is, the emitter is very heavily doped to maximize emitter injection, and the collector is relatively lightly doped so that it can accommodate large voltage swings across its reverse-biased junction. While the electrical characteristics are similar in appearance, the forward characteristics show much greater gain, as expected.
If both junctions are reverse biased, the transistor behaves like an open switch, with only the p-n junction reverse leakage currents flowing. If both junctions are forward biased, there is injection of carriers into the base region from both sides, and a low resistance is presented to current flow in either direction: the transistor behaves like a closed switch, and the base stores the injected charge.
BJTs can be used to provide linear voltage and current amplification: small variations of the base-emitter voltage and hence the base current at the input terminal result in large variations of the output collector current. Since the transistor output has the appearance of a current source, the collector can drive a load resistance and develop an output voltage across this resistance (within the limits of the supply voltage). The transistor can also be used as a switch in digital logic and power switching applications, switching from a high-impedance ‘off’ state in cut-off, to a low-impedance ‘on’ state in saturation. In practice, full saturation conditions of base-collector forward biased are generally avoided, to limit the carrier storage in the base and reduce the switching time. Such BJTs find application in analog and digital circuits and integrated circuits, at all frequencies from audio to radio frequency. For higher frequencies, such as microwave applications, heterojunction bipolar transistors (HBTs) are used.
HBTs are bipolar junction transistor which incorporate a wide band gap emitter, where the emitter-base junction is a heterojunction between semiconductors of different energy band gaps. The following are typical materials for HBTs: aluminum-gallium-arsenide (AlGaAs)(emitter)/gallium-arsenide (GaAs)(base); aluminum-indium-arsenide (AlInAs)/indiumgallium-arsenide (InGaAs); Si/silicon-germanium (SiGe); and indium-gallium-phosphide (InGaP)/GaAs, indium-phosphide (InP)/InGaAs. The wider band gap of the emitter significantly reduces the injection of majority carriers from the base to the emitter, thus maximizing the desired injection of carriers from the emitter to the base. This eliminates the requirement for a heavily doped emitter to achieve the same result, and consequently allows the based doping to be increased. An increase in base doping is desirable from a device viewpoint, as the base resistance can be reduced significantly. This leads to an improvement in the high-frequency performance of the transistor. HBTs are typically used at radio- and microwave frequencies, in integrated circuits (ICs), power applications, optoelectronic ICs, etc.
Compound semiconductor (e.g., GaAs, InP, etc.) HBTs play an important role in present day communications systems. They have been used extensively for power amplifiers in cell phones due to superior efficiency (i.e., longer battery life) and improved linearity (i.e., less distortion and longer operation range) in comparison to standard Si transistor technology. Also, such compound semiconductor HBTs are used in ultra-high speed digital ICs (i.e., operating at 10 Gigabit/sec) for fiber optic communications systems for telecom and Internet backbone transmission. Future generation fiber optic systems are targeted for 40, 80 and 160 Gigabit/sec applications that are well beyond the speeds of silicon (Si) IC technologies. In addition, HBTs may be used in phased-array radar and very high frequency terrestrial and satellite communication systems, and the reliability of HBT devices is not sufficient to incorporate these ICs into such applications, primarily due to the limitations of present HBT process technologies.
HBTs manufactured from compound semiconductor epitaxial layers including AlGaAs/GaAs, InGaP/GaAs, AlInAs/InGaAs, and InP/InGaAs have produced the world's fastest semiconductor transistors with cut-off frequencies of several hundred GigaHertz (GHz) and operating IC speeds above 80 GHz. See, for example, M. Rodwell, “Transferred Substrate InP HBT Technology”, Proceedings from the International Symposium on Indium Phosphide and Related Materials, Williamsburg, Va., 286, IEEE Press (2000). Compound semiconductor HBTs are of great commercial interest for very high-speed optical fiber digital communication systems operating at and above 10 Gigabit/sec, in microwave and millimeter-wave transmitters and receivers, and in high-power X-band (10 GHz) microwave radar systems. Recently, the intrinsic cut-off frequencies of Si bipolar junction transistors (BJTs) and SiGe HBTs have increased to the range of 100 GHz by submicron scaling of the emitter dimensions with reported emitter stripe widths as small as 0.25 μm. However, Si BJTs and SiGe HBTs suffer from several performance disadvantages in comparison to compound semiconductor HBTs, including, for example, low collector breakdown voltages and the inability to integrate passive components in ICs including resistors, capacitors, and inductors due to the glossy, conductive Si substrate. Therefore, HBTs fabricated from compound semiconductor layers grown on semi-insulating substrates are expected to continue to dominate the commercial market in very high-speed digital ICs and in very high-frequency radio frequency (RF) applications.
The schematic cross-section of a typical prior art compound semiconductor HBT that has been previously fabricated in a number of industrial, government, and academic research laboratories is shown in FIG. 1, having base 19, emitter 17 and collector 10 contacts. Such an N-type/p-type/n-type (n-p-n) HBT epitaxial wafer structure may be grown by Molecular Beam Epitaxy (MBE) or by Metal Organic Chemical Vapor Deposition (MOCVD) on a semi-insulating substrate 11. The epitaxial layers for the n-p-n HBT structure shown in FIG. 1 are conventionally grown in the following sequence: (1) highly doped n+ subcollector 12, (2) low doped n collector 13, (3) highly doped p+ base 14, (4) wide bandgap n emitter 15, and (5) highly doped n+ emitter contact 16. In some cases, the wide bandgap collector region 13 is used to improve the collector breakdown voltage.
The processing of the n-p-n HBT relies upon the use of the emitter metal contact 17 to serve as an etch mask to remove the emitter material down to the base layer 14. The area of the emitter p-n junction is defined by the emitter metal contact wherein the emitter metal is used to form lateral emitter undercuts 8 by wet chemical etch during the etch down to the base layer 14. For small area emitter p-n junction HBTs, Reactive Ion Etching (RIE) is sometimes first used to vertically etch the emitter semiconductor material followed by a wet etch to form the lateral emitter undercuts 8. This HBT process results in the so-called “T-shaped” emitter structure, and allows for a convenient method to obtain self-alignment of the base and emitter contacts by shadow evaporation of base metal 18 over the emitter metal 17.
A magnified schematic cross-section of the etched emitter p-n junction and emitter and base metal contacts is shown in FIG. 2. As shown, the base and emitter metal contacts will not bridge and hence short circuit as long as the base metal thickness is less than the vertical height of the semiconductor layer removed during the emitter etch (i.e., the combined thickness of wide bandgap n emitter 15 and highly doped n+ emitter contact 16), thereby providing vertical openings 22 between the base and the emitter metals. The separation between the base metal and semiconductor emitter p-n junction (i.e., at emitters 15 and 16) is determined by the emitter undercuts D 8 produced by lateral wet etching during the etch to the base layer.
The advantages of this simple HBT process are several-fold. Sub-micron spacing between base metal 18 and emitter p-n junction 15 can be readily achieved without the need for realignment of the base contacts by use of high-resolution projection photolithography. The narrow separation of the emitter undercuts 8 between the base metal contacts and emitter p-n junction also reduces the base access resistance that is an important parasitic component determining the RF performance of the n-p-n HBT. For example, the total base resistance, RB, for two base finger contacts straddling an emitter contact can be expressed generally as:RB=RBcon+RBaccess+RBint  (1) and more specifically as:RB=Rcon/2L+RBsheet D/2L+RBsheet W/12L  (2) where RBcon is the base metal contact resistance in ohms, RBaccess is the resistance drop between the base contact and the emitter semiconductor in ohms, RBint is the intrinsic resistance drop of the base under the emitter semiconductor in ohms, Rcon is the specific base metal contact resistance in ohmicrons, RBsheet is the two-dimensional base sheet resistance in ohms, D is the emitter undercut of the emitter metal in microns, W is the width of the emitter contact stripe in microns, and L is the length of the emitter contact stripe in microns. The importance of minimizing the emitter undercut D between the base metal contact and the emitter p-n junction is readily seen from Equation (2). For a typical high frequency n-p-n HBT design, the emitter stripe width W=1 μm. Therefore, if D=W/6=0.1667 μm, the total base resistance, RB, will be twice that of the intrinsic base resistance value assuming the base contact resistance is relatively small.
The effect of the total base resistance RB on the maximum oscillation frequency of an HBT for an IC can be expressed as:Fmax=(Ft/8πRBCT)1/2  (3) where Fmax is the maximum oscillation frequency which defines the highest possible operating frequency for an IC in Hertz (Hz), Ft is the transit time frequency in Hz, RB is the total base resistance in ohms, and CT is the total of the emitter and collector junction capacitances in farads. From Equation (3), it is evident that in order to achieve the highest Fmax value, the total base resistance, RB, and emitter and collector junction capacitances must be reduced by lateral (or horizontal) device scaling and the transit time frequency Ft should be reduced by vertical device scaling.
Although the “T-shaped” emitter HBT has resulted in ICs with world record speeds in the research laboratory, they suffer from several different manufacturing and processing problems that will ultimately limit their use in commercial high-speed IC applications. One such problem is the difficulty in controlling the emitter undercuts 8 by the edge of emitter metal 17 and the surface edge profile of the emitter p-n junction at emitter layers 15 and 16, as illustrated in FIG. 2. The difficulty encountered in using the emitter contact metal 17 for the emitter etch mask is caused by the enhanced electrochemical etch rate under the emitter metal. The emitter metal mask 17, the electrolyte formed by the chemical etchant, and the semiconductor surface (at 14, 15 and 16) form a galvanic cell due to the difference in the surface potential voltages of the metal and semiconductor. The resultant ionic current flow in the electrolyte etchant greatly accelerates the lateral etch rate of the semiconductor (at 15 and 16) under the emitter metal mask 17. Such enhanced lateral etch rates increased to as much as 500% over the normal vertical etch rate of the semiconductor covered by either photoresist or dielectric (e.g., silicon nitride (Si3N4) or silicon dioxide (SiO2) masks have been observed. This enhanced lateral etch rate under emitter metal 17 makes it extremely difficult to reproduce the emitter undercut of emitter metal 17 that is a critical parameter for RF performance of the HBT.
Also, the emitter undercut impedes the ability to deposit a conformal dielectric coating of Si3N4 and/or SiO2 that is considered to be essential for proper passivation of the emitter p-n junction. It is often seen that the deposition of dielectric or polymer films 9 leads to formation of voids 21 at the critical emitter p-n junction due to the narrow opening H 22 between the base 18 and emitter 17 metals. The inability to completely fill the emitter undercut can result in significantly reduced reliability and lifetimes of the HBT device, thereby precluding their use in many IC applications. This severe problem is further discussed below.
Another significant disadvantage to the “T-shaped” emitter HBT process is that it also greatly impedes process control since the undercut of the emitter metal is hidden from the surface. This makes it virtually impossible to accurately measure the undercut 8 in an HBT semiconductor process line. Meteorology tools such as Scanning Electron Microscopy (SEM) and Atomic Force Microscopy (AFM) are normally used to measure critical dimensions in semiconductor processing to obtain good process control and high IC yields. However, AFM cannot be used to measure the emitter undercut in the “T-shaped” HBT process because the AFM probe tip cannot penetrate below the emitter metal in the emitter undercut region. Also, SEM imaging of a tilted wafer cannot be used to accurately measure the emitter undercut due to the shadowing effect of the emitter metal in the collection of secondary electrons.
Another difficult and potentially fatal HBT reliability problem results from the use of conventional hydrochloric acid (HCl)-based wet etch chemistries to selectively etch the emitter layers containing AlInAs, InP, or InGaP regions while stopping at InGaAs or GaAs layers that form the p-type base layer. Selective etches are often used in the emitter etch process to prevent over-etching into the base region that would lead to variations in the base resistance and thus greatly reduce IC yields. The kinetics for etching with HCl-based wet chemical etches is reaction rate limited leading to highly anisotropic etch profiles. The observed etch rates are significantly slower on the low index (111A), (211A), or (311A) Ga-terminated crystal planes which contain the lowest densities of bonding electrons. Thus, the resultant etch profile for the semiconductor emitter p-n junction will have reentrant etch surfaces defined by these low index crystal planes along one of the directions of the emitter metal stripe.
The problem of properly passivating the emitter junction with a reentrant semiconductor surface is illustrated in FIG. 2. Plasma-Enhanced Chemical Vapor Deposition (PECVD) is conventionally used to deposit refractory dielectric films such as Si3N4 or SiO2 or silicon oxynitride (SiOxNy) for p-n junction passivation in compound semiconductor devices. In the “T-shaped” emitter HBT process, however, there is a very narrow opening H 22 between the base metal 18 and emitter metal 17 in which the plasma gas can flow to fill in the emitter undercut 8. In addition, the base metal 18 and/or emitter metal 17 serves as a RF shield effectively screening the plasma and decreasing the ion density in the vicinity of the contacts. This leads to incomplete PECVD dielectric coverage under the emitter metal 17 in the undercut 8 resulting in voids 21 at the critical emitter p-n junction. The lack of complete dielectric passivation of the emitter p-n junction will severely degrade the reliability of the HBT leading to short device lifetimes that will preclude their use in many high-speed IC applications.
The inability to properly passivate the emitter p-n junction with a dielectric (e.g., Si3N4, SiO2, SiOxNy, etc.) using PECVD has led some researchers to try depositing polymer films 9 such as polyimide (manufactured by DuPont) or Bis Cyclobutyl Butene (BCB) (manufactured by Dow Chemical) or spin-on glass to fill in the emitter undercut 8. However, it is still often observed that these polymer films 9 cannot always penetrate into the undercut 8 region through the narrow opening H 22 due to the surface tension of the polymer films. This, too, directly results in the formation of voids 21 at the critical emitter p-n junction that greatly decreases the HBT device reliability. Moreover, even if the polymer film 9 could fill in the emitter undercut 8, the critical problem of emitter p-n junction passivation is not solved. That is, these polymers are known to contain and are permeable to water vapor. Thus, water vapor can diffuse to the emitter p-n junction and further oxidize the semiconductor surface leading to increasing base surface recombination currents that will result in eventual HBT device failure.
Another disadvantage to these polymer films is that they are not true passivation films since they do not form strong chemical bonds with the semiconductor surface. For instance, it is well known that compound semiconductor surfaces contain a thin layer (1-3 nm) of native oxides formed from the constituent semiconductor elements during processing. In the case of spun-on polymer films, these layers only serve to overcoat the semiconductor native oxides and do not stabilize the semiconductor surface from further decomposition through oxidation in the presence of water vapor. This water vapor oxidation process of the semiconductor surface can be thermally-activated by heat caused by device power dissipation and/or can be electrically-activated by current flow at the surface of the emitter p-n junction. For the case of PECVD dielectric films, the deposition process actually removes the native oxides by chemical reaction with atomic hydrogen (H), which is present in plasma gas, before forming stable nitrogen (N) or oxygen (O) bonds with the semiconductor surface. These refractory dielectric films also form a hermetic seal preventing water vapor from reaching the semiconductor surface—water that can lead to deterioration of the emitter p-n junction and degrade the HBT's reliability.
These aspects of emitter p-n junction passivation are especially critical for very high frequency HBTs since ICs will operate at very high current densities and high junction temperatures. The emitter perimeter surface area to active p-n junction area ratio is also much larger in small-area, high cutoff frequency HBTs leaving them particularly susceptible to enhanced base surface recombination currents resulting in lower current gains. Thus, the use of refractory Si3N4 or SiO2 dielectric films for emitter p-n junction passivation is considered to be an essential and critical aspect for HBT device reliability and must be incorporated in the HBT process technology.
Another very important processing step for proper passivation of the HBT emitter p-n junction is the inclusion of a non-conducting, depleted and thinned emitter region or emitter “ledge” on top of the extrinsic base surface adjacent to the conducting emitter layer. See, R. J. Malik et al., “Self-Aligned Thin Emitter Heterojunction Bipolar Transistor (SATE-HBT) with Current Gain Independent of Emitter Area”, Electron. Lett., 25, 1175 (1989) and [Nortel REFERENCE]. This is a required process step to prevent minority carrier electrons injected into the base from recombining at surface states that would occur if the extrinsic base surface were exposed during the etch process. HBTs fabricated without this depleted ledge have been found to have seriously degraded operating lifetimes due to surface recombination. Therefore, all current industrial HBT manufacturing processes include this depleted ledge to produce HBTs with good reliability and long operating lifetimes. The formation of the depleted emitter ledge is normally accomplished by thinning the semiconductor emitter layer by a timed wet chemical etch which stops approximately 10-20 nm before reaching the base layer. For a non-self-aligned HBT process, the base metal is deposited through a shallow trench etched through the depleted emitter “ledge” that is defined using photolithography.
Next, the process steps used to form metal ohmic contacts to the HBT often determine the overall yield of functional discrete devices and ICs. Compound semiconductor process technology relies upon the use of gold-based (Au-based) metal contacts typically deposited by evaporation through a patterned photoresist mask that is defined by photolithography. The excess metal is removed by chemically dissolving the photoresist underneath the metal in what is known as a “lift-off” process. This is because conventional wet chemical and plasma etches for gold (Au) and related metals will also aggressively etch compound semiconductors such as GaAs and InP and are thus not compatible in this process technology. This can be compared to Si process technology where metal contacts are normally defined by blanket deposition of the metal by evaporation or sputtering and subsequent reactive ion etching (RIE) using a patterned photoresist mask.
The compound semiconductor metal lift-off process suffers from several disadvantages. For example, the resultant metal profile is often found not to have a flat topped surface but rather has high extending metal edges 28 (or “wings”) typically on one side of the metal feature 36, such as the emitter metal, as illustrated in FIG. 3. This is caused by the deposition geometry of the thermally heated or electron beam heated Au evaporation source, as depicted in FIG. 4. In FIG. 4, it is shown that the direction of the evaporated metal from the crucible 42 is along a vector Z 44 at an incident angle θ 47 with respect to the surface normal of the substrate 41. Incident angle θ 47 may be calculated as follows:θ=tan−1(X/Y)  (4) where θ is the incident angle 47, Y is the surface normal distance from the evaporated metal crucible 42 to the substrate 41, and X 46 is the lateral distance which the incident beam has diverged from the surface normal of the substrate 41. This results in some metal being deposited on the sidewall of the photoresist pattern that forms the extending metal edges 28 (or “wings”) (FIG. 3) on at least one edge of the metal, which can be as high as the thickness of the photoresist film. This is especially problematic when depositing thick metal layers or when defining narrow metal stripes with widths less than or equal to 1 micron. The high metal edges have a tendency to break off during subsequent process steps that can result in short circuits in the transistor structure that can greatly decrease discrete device and IC yields.
The following describes some known HBT manufacturing and processing methods. For example, Contrata et al. U.S. Pat. No. 5,943,577 (Contrata) discloses a method of making HBT structures having air and implanted isolations to uniformly etch a semiconductor layer regardless of an ultimate circuit configuration. More specifically, Contrata discloses a method of manufacturing a semiconductor device whereby a semiconductor layer having a device forming region is first formed on substrate. Then, a region other than the device forming region is changed into an insulator, and a conducting path is left across the semiconductor device to electrically connect the semiconductor device with an adjacent semiconductor device. Subsequently, the device forming region is etched on the condition that the conducting path is left. Finally, the conducting path is disrupted after the etching process. Thus, the semiconductor device and the adjacent semiconductor device are left in electrical contact via the conducting path during the etching process. Further, complete isolation between the semiconductor devices is carried out by disrupting the conducting path after the etching process.
Lammert U.S. Pat. No. 5,804,487 (Lammert) teaches a method of fabricating high beta HBT devices. Generally, Lammert discloses a method for controlling the spacing between the emitter mesa and the base ohmic metal of an HBT to obtain a relatively high gain (beta) with a low-parasitic base resistance. After the emitter, base and collector layers are epitaxially grown on a substrate, a sacrificial layer is deposited on top of the emitter layer. The emitter mesa is then patterned with a photoresist using conventional lithography, and subsequently, the sacrificial layer is etched to produce an undercut. Next, the emitter layer is etched and a photoresist is applied over the entire device. The top layer of the photoresist is then patterned with a conventional process for lift-off metallization, such that the final resist profile has a reentrant slope. Next, the base ohmic metal is deposited and then lifted off by dissolving both the second layer of photoresist, as well as the original photoresist over the emitter mesa. The sacrificial layer is stripped using an isotropic etch leaving a base ohmic metal region surrounding an emitter mesa at a spacing that is determined by the initial undercut of the sacrificial layer. In an alternate embodiment of the invention, Lammert discloses a method for controlling the spacing between the base ohmic metal and an emitter ohmic metal.
Oki et al. U.S. Pat. No. 5,892,248 (Oki) discloses a method for fabricating an HBT having self-aligned base metal contacts using a double photoresist layer. According to Oki, this process requires fewer steps than other methods, while minimizing damage to the active emitter contact region. In particular, a photoresist is used to form the emitter mesa which is left on while a double polymethylmethacrylate (PMMA) and photoresist layer is applied. The triple photoresist combination is patterned to create a non-critical lateral alignment for the base metal contacts to the emitter mesa, which permits selective base ohmic metal deposition and lift-off. By utilizing the double photoresist as opposed to a metal or dielectric for masking, an additional photolithography step and etching step is eliminated. By eliminating the need for an additional etching step, active regions of the semiconductors are prevented from being exposed to the etching step and possibly damaged.
Hafizi U.S. Pat. No. 5,729,033 (Hafizi) teaches a fully self-aligned submicron HBT and a method of fabricating such an HBT. The fabrication process of Hafizi includes lattice matched growth of subcollector, collector, base, emitter, and emitter cap layers in sequential order on a semi-insulating semiconductor substrate, with the formation of an emitter cap mesa, an emitter/base/collector mesa and a subcollector mesa. Dielectric platforms are then formed extending the base/collector layers laterally and forming sidewalls on the sides of emitter cap mesa and the sides of the extended base/collector layers. Next, undercuts are etched into the emitter layer and the upper portion of the subcollector layer. This forms an overhang on the emitter cap mesa with respect to the emitter layer and an overhang on the base/collector layers with respect to the upper portion of the subcollector layer. The emitter, base and collector contacts are simultaneously formed, with the base contact aligned to the edge of the emitter cap overhang and the collector contact aligned to the edge of the base/collector layer overhang.
Dubon-Chevallier et al. U.S. Pat. No. 5,412,233 (Dubon-Chevallier) discloses an HBT and a process for producing an HBT. Such a process comprises the known steps (or stages) consisting of producing layers forming the collector, base and emitter, as well as collector, base and emitter ohmic contacts. The emitter producing stage consists of depositing, on the base layer, two superposed layers making up the emitter, the first of which is a thin layer made up of a first material having a large energy gap, and the second made up of a second material also having a high energy gap. The base ohmic contact is then deposited on the first layer of the emitter.
Matsuoka et al. U.S. Pat. No. 5,717,228 (Matsuoka) discloses a self-aligned HBT which includes a semiconductor substrate having the (100) plane as a main surface, and at least a collector region, a base region, and an emitter region having a bandgap greater than the base region. According to Matsuoka, the emitter region has an under-cut mesa structure and its crystal orientation is defined in a direction other than that parallel to the (011) direction. The transistor does not have any outwardly slanted structure in either the (001) direction or the (011) direction that could cause current leakage between the emitter and base, thereby providing a transistor with improved electric isolation between the emitter and base, although it is self-aligned.
Bayraktaroglu U.S. Pat. No. 5,471,078 (Bayraktaroglu) teaches a self-aligned HBT and a method of fabricating the same including the epitaxial growth of collector, base and emitter layers, allowing for self-aligned emitter-base contacts to minimize series base resistance and to reduce total base-collector capacitance. More particularly, the method according to Bayraktaroglu is such that the epitaxial in situ doped collector, base and emitter layers are grown over an entire semi-insulating GaAs substrate. The wafer is then covered with a metal emitter contact layer followed by an insulator layer. Next, the emitter areas are patterned and etched down to the emitter epilayer, sidewalls are formed on the resulting islands and the exposed portions of the emitter epilayer are chemically etched down to the base epilayer. Finally, base contacts are deposited and the emitter contact is covered with deposited metal.
Sakai et al. U.S. Pat. No. 5,698,871 (Sakai) discloses an HBT that includes a compound semiconductor substrate, a collector layer disposed on the compound semiconductor substrate, a base layer disposed on the collector layer, the base layer being a semiconductor having a band gap energy and including an internal base region and an external base region, and an emitter layer disposed on the base layer and being a semiconductor having a band gap energy larger than the band gap energy of the semiconductor of the base layer. According to Sakai, the base layer is larger in area than the emitter layer by the external base region. The external base region is sandwiched by insulating films at the external base region. Therefore, without ion-implantation to make the resistance of the collector layer below the external base region higher, i.e., without increasing the base resistance, the base-collector capacitance is reduced, resulting in an HBT having an improved high frequency gain.
Yang et al. U.S. Pat. No. 5,981,985 (Yang) teaches an integrated HBT with minimized base-collector capacitance, a sub-collector region is formed as a mesa on a substrate, a collector contact is to the sub-collector mesa region, a lightly-doped collector region and a base region extend from the mesa onto the substrate, and a base contact and its via hole for interconnection are off the mesa, with minimal overlap with the sub-collector region. The latter may be termed a buried selective sub-collector region. Transistors such as this can be used as integrated switching devices and microwave devices, e.g., in wireless communications, satellite direct broadcast systems, automobile collision avoidance systems, global positioning systems, and other high-frequency applications.
Delaney et al. U.S. Pat. No. 5,569,944 (Delaney) discloses, generally, and in one form of the invention, a method for making an HBT comprising the steps of forming a compound semiconductor material structure comprised of a plurality of layers, wherein at least one of the layers comprises a first material (e.g., GaAs) and at least one of the remaining layers comprises a second material (e.g., AlGaAs), and etching the layers comprised of the first material with an etchant that does not appreciably etch the layers of the second material. A surprising aspect of this invention is that no additional etch stop layer was needed in the material structure, because etchants were used that stop on the wide band gap emitter layer (e.g., AlGaAs) usually found in HBTs despite the similarity of the AlGaAs and GaAs layers. According to Delaney, an advantage of this method is that a reference point for timing subsequent etches is established at a point other than the top of the uppermost of the layers, thereby improving the accuracy with which the depth of the subsequent etching can be controlled, which directly relates to more producible and higher yield HBTs.
As discussed above, HBT manufacturing and processing is not new. However, it does suffer from significant disadvantages, as described herein, which greatly hinder the applicability of resulting HBTs to many IC applications. The present invention overcomes these disadvantages by providing a precise means of manufacturing compound semiconductor HBTs having self-aligned emitter and base metal contacts with submicron spacing using a dielectric-assisted metal liftoff process. Such a novel process provides precise submicron spacing and flat topped surfaces free from disadvantageous metal “wings”, improves the reproducibility of the HBT manufacturing process by eliminating the possibility of over-etching to the base layer, and provides an etched emitter p-n junction with the appropriate surface profile that can be properly passivated with a dielectric (e.g., Si3N4, SiO2, SiOxNy, etc.) for excellent device reliability.
Moreover, the present invention provides significant advantages not present in previous processes. Some of these advantages include elimination of undercutting the emitter metal during etching, which provides more reliable passivation of the emitter mesa p-n junction, having a lateral etch rate that defines the emitter mesa-base contact separation substantially equal to the vertical etch rate to greatly enhance the HBT process control, utilizing an emitter semiconductor having a built-in Phosphorous-containing layer to prevent over-etching (i.e., into the base) and to provide a depleted emitter “ledge” for greater HBT reliability, completely encapsulating the emitter metal with a dielectric insulating film to, inter alia, prevent sputtering of the emitter contact during RIE, and providing for fabrication of arbitrarily small emitter stripe widths (i.e., down to sub-micron dimensions), which increases the cut-off frequencies of the HBTs to several hundred GigaHertz (GHz).